1. Field of the Invention
The present invention is directed to phase locked and delay locked loops and, more particularly, to the delay line used in such loops.
2. Description of the Background
A phase locked loop is a circuit designed to minimize the phase difference between two signals. When the phase difference approaches zero, or is within a specified tolerance, the phase of the two signals is said to be “locked”. A delay locked loop is similar to a phase locked loop, but instead of producing an output signal which has the same phase as an input or reference signal, the delay locked loop passes a reference signal or input signal into a delay line, and the output of the delay line has some predefined phase delay with respect to the reference or input signal.
Phase locked loops (PLL's) and delay locked loops (DLL's) are widely used circuits where it is necessary to have two signals which have a known relationship to one another. For example, when transmitting information from a sending device to a receiving device, it is necessary to have the local clock of the receiving device in sync with the clock of the sending device so that the information can be reliably transmitted. A PLL may be used for that purpose. Both PLL's and DLL's have been used for a long period of time, and numerous analog examples of these circuits can be found in the literature and in many devices.
Both PLL's and DLL's may be implemented either by analog components or digital components. In an analog loop, a delay chain is used to adjust delay and each element in the delay chain has its delay varied by analog bias voltages supplied by a phase detector. In a digital loop, rather than adjust the delay of, for example, a transistor, the delay is adjusted based on the number of delay stages that are included in the delay chain. Analog loops have continuous delay adjustments whereas digital loops adjust delays in discreet steps. As a result, one advantage of an analog loop is that the jitter is very low compared to the step jitter of a digital loop.
It is also known to implement loops in phases. For example, U.S. patent application Ser. No. 09/585,035, filed Jun. 1, 2000, entitled Digital Dual-Loop DLL Design Using Coarse and Fine Loops illustrates a circuit in which the delay line is comprised of both a coarse loop and a fine loop. The coarse loop is designed to produce an output signal having a phase variation from an input signal within a course delay stage while the fine loop is designed to produce an output signal having a phase deviation from the input signal which is substantially smaller than the deviation of the coarse loop. The coarse loop is designed to bring the output signal to a near phase lock condition, or phase delayed condition, while the fine loop is designed to achieve a locked condition. Thus, a dual-loop (coarse and fine loops) all digital PLL or DLL can provide a wide lock range while at the same time still providing a tight lock within reasonable time parameters.
There are several ways to implement the fine delay tap used in a fine loop. For example, one implementation embodies load-adjusting using variable load capacitors. Another implementation is to provide both a fast path and a slow path using slightly different sized devices. The first method has little intrinsic delay and almost constant delay over process, voltage and temperature (PVT) variations. In contrast, the second method has a large intrinsic delay but provides better tracking for delay variations. Thus, a tradeoff must be made which is driven by the design parameters of the final device. Accordingly, a need exists for a DLL and PLL that have a large locking range, tight locking characteristics, little intrinsic delay, low power dissipation and good tracking over PVT variations.